RISC-V Based SoC Design, Verification, and Validation in One Hour

Presented at DVCon U.S. 2021 RISC-V brings a new wave to SoC development. Creating a fully validated design is an arduous process that takes several teams working together. Often the flow is a waterfall model where the specification is transformed in various stages of development. Sometimes aspects such as verification and validation are an afterthought. In order to speed up the process and get better quality of results, all aspects must be considered upfront. By: Anupam Bakshi, Agnisys, Inc. Abhishek Bora, Agnisys, Inc. https://dvcon.org https://dvcon-proceedings.org