Mastering Static Timing Analysis (STA) | In-Depth Marathon Theory Episodes

Run The Full Marathon: Mile1:    • Mastering Static Timing Analysis (STA) | I...   Mile2:    • Mastering Static Timing Analysis (STA) | I...   Mile3:    • Mastering Static Timing Analysis (STA) | I...   Mile4:    • Mastering OperTimer STA EDA Tool  | In-Dep...   In this comprehensive video, the host explores Static Timing Analysis (STA) for VLSI design. They introduce the STA Marathon Episode and guide viewers through the episode index. The video covers the foundational aspects of STA, its significance in ASIC/SOC design, and the principles behind its operation. It delves into various STA components, Timing Analysis Paths, Delay calculations, Clock Latency, and False Paths. The video also addresses Clock Uncertainty, Process-Temperature-Voltage Corners, and On Chip Variations (OCV), offering a holistic perspective on STA for VLSI design. In this episode we have discussed on the theories of STA i.e. Static Timing Analysis in VLSI in the below chapters: 00:00:00 Introduction To STA Marathon Episode 00:00:33 First Episode Index 00:01:16 Talk About Series Skeleton 00:03:02 STA Introduction 00:04:25 Types of Timing Analysis in VLSI 00:06:53 Dynamic Timing Analysis 00:11:10 Static Timing Analysis 00:13:25 Why STA is Preferred for ASIC/SOC ? 00:15:47 How STA Works so fast ? 00:18:38 Need of STA Concepts : When the STA Tool can do everything ! 00:20:20 Intermission-1 00:20:23 Second Episode Index Chapters 00:21:31 STA in the Design Flow in ASIC/SOC 00:23:55 STA Engine I/O At a Glance 00:26:36 STA Output Terminologies 00:28:04 Timing Expectation Vs Reality Check 00:29:11 What is a Timing Analysis Path ? 00:30:14 Types of Path under STA Scanner 00:31:41 What is Directed Acyclic Graph (DAG) 00:33:19 Directed Acyclic Graph (DAG) Example 00:35:57 Maximum & Minimum Path Concept 00:37:19 Intermission-2 00:37:21 Third Episode Index Chapters 00:38:17 STA Delays 00:39:34 Propagation Path Delay 00:42:36 Physical Path Delay 00:44:41 Prelayout Net Delay Calculation 00:46:41 Designer Defined Delay : Pre Layout 00:47:41 Post Layout Net Delay : RC Back Annotation 00:49:50 Cell Delay Calculation 00:50:49 Rise and Fall Slew Concept 00:54:33 Rise Slew Vs Delay from .lib 00:59:03 Fall Slew Vs Delay from .lib 01:01:26 Intermission-3 01:01:29 Episode Four Index Chapters 01:02:29 Clock Latency and Skew 01:05:13 Setup & Hold Time Concept 01:09:16 Setup Constraints from Timing .lib 01:15:14 Hold Constraints from Timing .lib 01:18:26 Setup Equation Concept 01:21:45 Hold Equation Concept 01:23:13 Multi Cycle Path Concept 01:24:22 Half Cycle Path Concept 01:25:58 Intermission-4 01:26:01 Fifth Episode Index Chapters 01:27:07 Types of False Path in STA Analysis 01:28:42 Asynchronous False Path in STA 01:29:58 Static False Path in STA : Recovery & Removal Time 01:32:06 Non-Functional False Path in STA 01:34:38 Clock Uncertainty Concept 01:36:48 Clock Uncertainty Quantification 01:37:46 Process-Temperature-Voltage Corners & Delay 01:40:07 Process-Temperature-Voltage Corners & Setup/Hold-Violation 01:41:05 On Chip Variations (a.k.a OCV) #vlsi #vlsitraining #vlsiprojects Open Timer Installation Video Link ::    • Complete Guide: Installing OpenTimer for S...   Open Timer Demo Video Link ::    • Unlocking Live VLSI Design Analysis with O...   Design Data is Accesed using TCL APIs :    • Demystifying TCL in VLSI: A Comprehensive ...   Courtesy: Music by BenSound.com Image by Tobias Dahlberg from Pixabay Image by OpenClipart-Vectors from Pixabay Image by Darwin Laganzon from Pixabay ELEX 7660 : Digital System Design 2018 Winter Term , Lecture - 8 Synthesis & Timing Analysis , Mark McDermott , The University of Texas at Austin , Lecture 21 STA - Static Timing Analysis : Gil Rahav ,Semester B’ , EE Dept. BGU. Static Timing Analysis in a nutshell , Frank de Bont OpenTimer Wiki