Mastering Static Timing Analysis (STA) | In-Depth Marathon Input Output File Formats Episodes

Run The Full Marathon: Mile1:    • Mastering Static Timing Analysis (STA) | I...   Mile2:    • Mastering Static Timing Analysis (STA) | I...   Mile3:    • Mastering Static Timing Analysis (STA) | I...   Mile4:    • Mastering OperTimer STA EDA Tool  | In-Dep...   This comprehensive video explores key aspects of the Standard Timing Analysis (STA) Marathon, beginning with the sixth episode's focus on Liberty Timing Library (.lib). The tutorial covers Liberty File creation, internal formats, and the significance of name tokens. Definitions of Header, LUT, Standard Cell, FF & Latch, and Scan Chain Cell are detailed with examples. An intermission introduces the Design Constraint File (.sdc) for the seventh episode. Constraints' rationale, frequently used commands, and the Directed Acyclic Graph (DAG) are discussed. The eighth episode introduces the SPEF PEX File (.spef), detailing post-layout parasitics and sections within a SPEF file. A third intermission leads to the fourth episode, covering Standard Delay Format (SDF) and TWF File. The SDF File's structure, limitations, and Timing Section details are explained, concluding with a snippet. The TWF File is briefly overviewed, providing viewers with a comprehensive understanding of STA essentials. In this episode we have discussed on the theories of STA i.e. Static Timing Analysis in VLSI in the below chapters: 00:00:00 Introduction To STA Marathon Episode 00:00:36 STA Input Output Files : Liberty Timing Library (.lib) 00:01:22 Sixth Episode Index 00:02:01 How Liberty File is Created ? 00:03:22 Cell Library (Liberty) Introduction 00:06:27 Liberty (.lib) Internal Format 00:07:28 Name Tokens & Their Meaning 00:10:52 Header Section :: Definition 00:12:50 LUT Section :: Definition 00:14:35 Standard Cell Section :: Definition 00:17:03 FF & Latch :: Definition 00:18:14 Scan Chain Cell :: Definition 00:20:02 Examples Intro 00:20:16 Header Section :: Example 00:24:31 Cell Begin & End ::Example 00:27:22 Cell Output-RiseDelay/LUT :: Example 00:29:07 Cell Output-Fall-Delay/LUT :: Example 00:30:25 Cell Output-RiseSlew/LUT :: Example 00:31:34 Cell Output-FallSlew/LUT :: Example 00:32:09 Intermission-1 : Design Constraint File (.sdc) 00:32:11 Seventh Episode Index Chapters 00:33:17 Why We Write Constraints ? 00:34:59 Design Constraint File Introduction 00:37:41 Frequently Used Design Constraint Commands 00:39:30 Some More Commands … 00:41:09 Recall the Directed Acyclic Graph (DAG) Concept 00:41:48 Arrival Time :: Input Delay 00:43:34 Required Arrival Time :: Output Delay 00:44:56 Rise/Fall Slew Design Constraint 00:46:09 Some More Applications …... 00:47:08 Intermission-2 : SPEF PEX File (.spef) 00:47:10 Eigth Episode Index Chapters 00:48:22 Introduction To SPEF (Standard Parasitic Extraction Format) 00:49:45 Post Layout Parasitics Visualization 00:51:47 Extraction : ASIC Design Flow 00:55:06 SPEF & The Entire Design 00:56:44 Various Sections of a SPEF File 00:57:49 Header Section 00:59:48 Name Map Section 01:02:02 Port Section 01:03:35 R/C/Cc :: D_NET Section 01:05:21 R/C/Cc :: CONN Section 01:07:03 R/C/Cc :: RES Section 01:08:30 R/C/Cc :: CAP Section 01:09:48 R/C/Cc Section :: Example 01:17:10 Standard Parasitic Extraction Format (SPEF) Snippet 01:19:22 Intermission-3 : Standard Delay Format(SDF) and TWF File 01:19:24 Episode Four Index Chapters 01:21:03 Introduction to SDF File 01:24:45 What is Inside the SDF File ? 01:26:05 Limitation of SDF File 01:28:30 SDF File Structure :: Header/Cell/Timing Sections 01:29:16 SDF File :: Header Section 01:34:30 SDF File :: Cell & It’s Type 01:36:23 SDF File :: Cell Instance 01:37:50 Timing Section :: DELAY / TIMINGCHECK 01:38:37 Timing Section :: PATHPULSE 01:40:47 Timing Section :: PATHPULSEPERCENT 01:41:31 Timing Section :: ABSOLUTE delay 01:43:28 Timing Section :: RTRIPLE format 01:44:40 Timing Section :: INCREMENT delay 01:46:02 Example of SDF File :: Snippet 01:47:38 TWF File in a NutShell Open Timer Installation Video Link ::    • Complete Guide: Installing OpenTimer for S...   Open Timer Demo Video Link ::    • Unlocking Live VLSI Design Analysis with O...   Design Data is Accesed using TCL APIs :    • Demystifying TCL in VLSI: A Comprehensive ...   #vlsi #vlsidesign #physicaldesign Courtesy: Music by BenSound.com Image by Tobias Dahlberg from Pixabay Image by OpenClipart-Vectors from Pixabay Image by Darwin Laganzon from Pixabay ELEX 7660 : Digital System Design 2018 Winter Term , Lecture - 8 Synthesis & Timing Analysis , Mark McDermott , The University of Texas at Austin , Lecture 21 STA - Static Timing Analysis : Gil Rahav ,Semester B’ , EE Dept. BGU. Static Timing Analysis in a nutshell , Frank de Bont OpenTimer Wiki