Mastering UPF : A Comprehensive Marathon Guide to Unified Power Format in VLSI Design

This comprehensive video series, UPF Marathon, provides a detailed exploration of Unified Power Format in VLSI design. The initial episode introduces UPF, emphasizing its significance in CHIP and SOC design. Covering UPF fundamentals, including annotations and benefits, the series progresses to advanced topics such as power domains, standard cell mapping, isolation cells, retention cells, and level shifters. Subsequent episodes address UPF in HDL simulation, supply functions, and power modes. The presenter responds to viewer questions, clarifying concepts like power domains and power-up/down sequences. The series concludes with an episode on digital buffers, level shifters, and a comparative analysis. Viewers gain a comprehensive understanding of UPF's crucial role in VLSI design through a structured and informative exploration across multiple episodes. Read The article @ Episode -1 : https://www.techsimplifiedtv.in/2024/... Episode -2: https://www.techsimplifiedtv.in/2024/... Episode -3: https://www.techsimplifiedtv.in/2024/... Episode -4 : https://www.techsimplifiedtv.in/2024/... We have discussed about UPF ( Unified Power Format ) in VLSI as below chapters: 00:00:00 Introduction to UPF Marathon 00:00:32 Beginning of EP-1 & Topic Index 00:01:14 UPF in today’s CHIP Design Scenario 00:03:47 How UPF is placed in SOC Design 00:04:48 What is UPF : In Detail 00:06:55 Three Major Types of UPF Annotations 00:07:54 Benifits of Using UPF in SOC Design 00:09:25 Standard UPF Terminologies 00:11:45 UPF Integration in Various Design Stages 00:13:44 Four Major Type of UPF Commands 00:15:16 Beginning of EP-2 & Topic Index 00:16:26 Power Domain Concept 00:18:58 Power Domain with Single Hierarchical Instance 00:20:22 Power Domain instance with Child Elements 00:22:54 Creating further Hierarchy 00:25:20 UPF Power Domain Creation Command 00:26:22 UPF Power Domain Creation Command : Example-1 00:27:34 UPF Power Domain Creation Command : Example-2 00:28:45 UPF Power Port, Power Net Creation Command 00:31:30 Beginning of EP-3 & Topic Index 00:32:33 UPF and Corresponding Standard Cells 00:33:20 UPF vs Standard Cells Mapping 00:34:49 Header/Footer Switch Cells & Corresponding UPF Command 00:36:37 Isolation Cells 00:38:05 Isolation UPF Command 00:39:51 Retention Cells/Flops 00:41:31 Retention UPF Command 00:42:53 Level Shifter Cells 00:45:28 Level Shifter UPF Command 00:46:32 Types of Level Shifter Cells 00:47:53 Power Domain & Above Mentioned Standard Cell Placement 00:49:07 Beginning of EP-4 & Topic Index 00:49:59 UPF and HDL Simulation 00:52:47 UPF Function Types 00:53:18 UPF Function Syntax 00:55:00 UPF Supply Query Functions 00:55:48 Supply Net Data Type in HDL 00:57:38 Supply Net In UPF 00:58:29 Switching Activity Interchange Format (S.A.I.F) 00:59:49 System-Verilog Package for UPF 01:01:47 VHDL Package for UPF :UPF Supply Net 01:02:19 VHDL Package 01:05:07 Beginning & Intro of EP-5 01:05:38 Viewer's Question 01:05:54 What is Power Mode ? 01:09:43 Popular Power Modes 01:11:49 What is Power Domain ? 01:14:55 Power-Up & Power-Down Sequence. 01:17:18 Summary 01:18:14 Beginning & Intro of EP-6 01:18:59 Viewer’s Question 01:19:32 Topic Index 01:20:16 What is a Digital Buffer ? 01:21:44 Types of Digital Buffers 01:23:28 What is a Level Shifter (a.k.a Translator) ? 01:24:36 Types of Level Shifters 01:25:54 Buffer Vs Level Shifter : Comparison 01:27:11 Buffer Vs Level Shifter : Example 01:28:59 SN74LV1T34 : Logic Level Shifter 01:30:41 Buffer Vs Level Shifter : Summary #vlsi #vlsitraining #vlsidesign Courtesy & Reference: Music By Bensound.com Image by Tide He from Pixabay Image by Darwin Laganzon from Pixabay Accellera UPF 1.0 Documentation