MACRO PLACEMENT | FLOORPLAN | CADENCE | INNOVUS | PHYSICAL DESIGN | ASIC | ELECTRONICS | VLSIFaB

#Vlsi #pnr #cts #physicaldesign #mtech #cadence #synopsys #mentor #placement #floorplan #routing #signoff #asic #lec #timing #primetime #ir #electromigration #interviewquestions #drc #lvs #erc #memory #clock #flipflop #digital #physicalverification #analog #verification #vlsi #companies #vlsi #career #slack #skew #macro #powerplanning #electronics #lowpower #delay #cell #Verilog #STA #UPF #cmos #chip #antenna #intel #silicon #semiconductor #pad #synthesis Macro Placement Tips The formula to calculate spacing between two macro is (width+spacing x number of pins /vertical routing layers) + spacing. It is better adding an additional spacing because you can avoid violation with the side of macros. 1. Place macros around chip periphery. 2. Consider connections to fixed cells when placing macros. 3. Orient macros to minimize distance between pins. 4. Reserve enough room around macros. 5. Reduce open fields as much as possible. 6. Reserve space for power grid. Macro(Memory) placement rules implementation hands on using cadence Innovus (Encounter soc). If you get any help from this video don't forget to like comment and subscribe the channel to get all the videos VLSIfab playlist are given below: pnr flow    • pnr   career guidance in vlsi field.    • career guidance in VLSI field   Timing and constraints (physical design)    • timing and constraints (physical design)   M.TECH project IN VLSI    • M.Tech  Project (schematic to layout) in c...   PHYSICAL DESIGN FLOW IN DIFFERENT TOOLS OF CADENCE AND SYNOPSYS    • Physical design flow in different tools of...