FLOORPLAN USING INNOVUS ( PART2/3) | PHYSICAL DESIGN | ASIC | ELECTRONICS | VLSIFaB

#Vlsi #pnr #cts #physicaldesign #mtech #cadence #synopsys #mentor #placement #floorplan #routing #signoff #asic #lec #timing #primetime #ir #electromigration #interviewquestions #drc #lvs #erc #memory #clock #flipflop #digital #physicalverification #analog #verification #vlsi #companies #vlsi #career #slack #skew #macro #powerplanning #electronics #lowpower #delay #cell #Verilog #STA #UPF #cmos #chip #antenna #intel #silicon #semiconductor #pad #synthesis floor planning in details using innovus (cadence) tool. It is the process to give platform for complete pnr. It is the continuation of my last video. Please like share and subscribe to get all the videos. This is the first major step in getting your layout done, and for me this is the most important one.Your floorplan determines your chip quality.At this step, you define the size of your chip/block, allocates power routing resources, place the hard macros, and reserve space for standard cells.Every subsequent stage like placement, routing and timing closure is dependent on how good your foorplan is. In a real time design, you go through many iterations before you arrive at an optimum floorplan.