From top to Transistors: opensource Verilog to ASIC flow
Go from HDL to physical CMOS layout right now with open-source tools, by following this HOWTO guide and demo. When things go well, the design can be converted to GDS for ASIC fabrication in a single step. I also show how we can dig deeper, using yosys, openlane and openroad, when the hardening processes isn't quite as simple. This is part of my journey through the zero to ASIC course, so I don't have all the answers, but have found some interesting bits already. Let me know if you see mistakes, or have hints! I'll be updating the ASIC playlist with more as I progress. ** Links of interest ** Details, written instructions, downloads: https://inductive-kickback.com/2023/0... My fork of the demo structure, with the Makefile used in the video: https://github.com/psychogenic/tt03-v... OpenLane: https://github.com/The-OpenROAD-Proje... TinyTapeout: https://tinytapeout.com/
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