Automatic Generation of SystemVerilog Models from Analog/Mixed-Signal Circuits: A Pipelined ADC

The webinar addresses how to extract SystemVerilog models automatically from analog/mixed-signal circuits, and perform efficient verification of mixed-signal SoC's using digital flows, such as UVM. It will introduce two modeling approaches, structural and functional, and demonstrate how these approaches work together using a pipelined analog-to-digital converter example. Website: https://www.scianalog.com/ Email: [email protected]