How much combinitorial logic is too much? Always block guide for beginners by FPGA professional.
Hi, I'm Stacey and in this video I discuss the difference between asynchronus and synchronus always blocks in verilog. When to use each, and how much combinitorial logic is too much?! Xilinx LFSR paper: https://www.xilinx.com/support/docume... Google form to give me your feedback: https://forms.gle/ssNwzTKiioj3RNHD9 Github Code: https://github.com/HDLForBeginners/Ex... Ending music: Faith by David van Niekerk • Faith (Ocean of Reverb Original) - David v... I'm on discord on the r/fpga server ( / discord , as Stacey, come say hi and chat all things FPGA! 0:00 Intro 0:50 Opening project in Vivado 1:43 Asynchronus: Intro 2:10 Asynchronus: Used for more space for combinitorial logic 2:37 Asynchronus: Why do we need to be aware of the amount of logic? 3:15 Asynchronus: How much is too much logic?! 4:00 Asynchronus: Inferred latches 4:54 Asynchronus: Blocking and non Blocking assign 5:10 Asynchronus: Summary 5:25 Synchronus: Intro and use #1, pipelining 6:06 Synchronus: use #2, memory for storing signals later 7:07 General notes: position in file 7:40 Example project: LFSR waveform 10:23 Synchronus: Summary 10:38 Outro Buy me a coffee to support my channel: https://www.buymeacoffee.com/fpgasfor...
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