Timing Constraints: How do I connect my top level source signals to pins on my FPGA?

Hi, I'm Stacey and in this video I talk about how to use timing constraints to connect up your top level port signals to pins! HDLforBeginners Subreddit!   / hdlforbeginners   Quartus Templates: Found by navigating to Edit - Insert Template with a file open in the Quartus Prime Text Editor. https://www.intel.com/content/www/us/... Templates I used: https://github.com/HDLForBeginners/Ex... Digilent master XDC files: https://github.com/Digilent/digilent-xdc More advanced timing concepts in this altera paper: https://www.intel.com/content/dam/alt... Google form to give me your feedback: https://forms.gle/ssNwzTKiioj3RNHD9 Ending music: Faith by David van Niekerk    • Faith (Ocean of Reverb Original) - David v...   I'm on discord on the r/fpga server (  / discord  , as Stacey, come say hi and chat all things FPGA! 0:00 Intro 0:27 Find your board user manual 0:43 Determine your device vendor 1:47 Find Clock pin on board 2:13 Create new constraints file 2:45 Language templates in Vivado 3:04 create_clock constraint 4:00 PACKAGE_PIN constraint 4:24 clock constraint summary 5:00 GPIO constraint example 5:37 IOSTANDARD constraint 6:07 Reset constraint example 7:04 Outro Buy me a coffee to support my channel: https://www.buymeacoffee.com/fpgasfor...