Ep 072: Memory Hierarchy Addressing Modes and SRAM versus DRAM Technology

After discussing memory maps and chip selects, let's revisit the memory hierachy and get an overview of the different types of addressing used at each level. After that, let's take a look at the different technologies used to implement two of the levels: main memory and the cache.

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Ep 073: Introduction to Cache Memory
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Ep 073: Introduction to Cache Memory

Capacitors are terrible at remembering data. But for this reason we continue doing it.
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Capacitors are terrible at remembering data. But for this reason we continue doing it.

Ep 067: Introduction to the Memory Hierarchy
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Ep 067: Introduction to the Memory Hierarchy

Ep 070: Designing an Active-Low Chip Select from a Memory Map
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Ep 070: Designing an Active-Low Chip Select from a Memory Map

VLSI - Lecture 8a: SRAM - Introduction
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VLSI - Lecture 8a: SRAM - Introduction

EEVblog 1752 - Texas Instruments SCREWED UP the NE5532!
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EEVblog 1752 - Texas Instruments SCREWED UP the NE5532!

Ep 068: Organization of a Simple Memory Device
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Ep 068: Organization of a Simple Memory Device

Ep 081: Introduction to the Stack Pointer
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Ep 081: Introduction to the Stack Pointer

Semiconductors explained in 16 mins | Chris Miller
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Semiconductors explained in 16 mins | Chris Miller

Ep 086: Introduction to Input/Output
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Ep 086: Introduction to Input/Output

Introduction to DRAM System
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Introduction to DRAM System

Casey Muratori – The Big OOPs: Anatomy of a Thirty-five-year Mistake – BSC 2025
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Casey Muratori – The Big OOPs: Anatomy of a Thirty-five-year Mistake – BSC 2025

Ep 069: Introduction to Chip Selects in a Flat Memory Model
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Ep 069: Introduction to Chip Selects in a Flat Memory Model

6 Horribly Common PCB Design Mistakes
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6 Horribly Common PCB Design Mistakes

SRAM vs DRAM : How SRAM Works? How DRAM Works? Why SRAM is faster than DRAM?
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SRAM vs DRAM : How SRAM Works? How DRAM Works? Why SRAM is faster than DRAM?

Introduction to Direct Memory Access (DMA)
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Introduction to Direct Memory Access (DMA)

Prof. Preeti Ranjan Panda | Runtime Co-optimisation in the Memory Hierarchy | VOMS 2017
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Prof. Preeti Ranjan Panda | Runtime Co-optimisation in the Memory Hierarchy | VOMS 2017

Ep 076: Set-Associative Caches
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Ep 076: Set-Associative Caches

Hardware Architect Answers Microchip Questions | Tech Support | WIRED
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Hardware Architect Answers Microchip Questions | Tech Support | WIRED

One Memory Bit SRAM - Georgia Tech - HPCA: Part 4
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One Memory Bit SRAM - Georgia Tech - HPCA: Part 4