How the AXI-style ready/valid handshake works

The ready/valid hardware data transfer protocol is simple and ingenious, providing flow control with only two control signals. The rules are very simple: data transfer only happens on the bus when both "ready" and "valid" are '1' during the same clock cycle. However, it may be tricky to implement this mechanism in VHDL. Read the full article about the ready/valid handshake on VHDLwhiz: https://vhdlwhiz.com/how-the-axi-styl... 09:17 ** Challenge: Pipelining with AXI-style ready/valid flow control To make learning VHDL fun, I've created a coding challenge where you can practice getting the ready/valid handshake right. In the competition, I provide a module with a self-checking testbench. The module works fine and runs through all the test cases. But the module's operation is complex and should be split over multiple clock cycles to ease timing. Your task is to convert the example module to a pipelined design that uses three clock cycles instead of one without limiting the throughput. It should still run through the same self-checking testbench. After one week, I will post a video explaining half of my proposed solution, which should make it easier. Finally, I will reveal my complete solution after two weeks and explain how it works. If you are viewing this video sometime in the future, the hint and solution videoes will already be waiting for you on the challenge page. You can still join the membership and take the challenge. Click here to read more about the VHDLwhiz Membership and join: https://academy.vhdlwhiz.com/membership Here's a direct link to the challenge page in the Membership portal (only accessible for members): https://academy.vhdlwhiz.com/products...