I Built a RISC-V CPU to Explain How Instructions Really Work

The video covers most of the RISC-V RV32I instructions (ECALL, EBREAK and CSR are skipped). This gives a good start for people starting to understand RISC-V ISA and the best way that I could figure out to understand that has been to understand how it translates to HW. Some diagrams (the ones showing how bits are extended are taken from here https://github.com/johnwinans/rvalp/r... This is a wonderful resource. At the end of this document you can also see RISC-V instruction cards summarizing all instructions in one pager. Topics Covered: (00:00) Building Blocks (06:30) Higher level language to assembly (11:00) RISC-V instruction set intro (12:31) Reg-Reg ALU instructions (18:50) Load instructions (22:42) Alu-Imm instructions (24:24) Store instructions (26:05) Branch instructions (29:00) Jump/JAL and JALR instructions (33:18) LUI instruction (36:16) AUIPC instruction (37:58) Control logic