Factory Registration macro's w.r.p.t System Verilog version of UVM

This video is all about the concept of factory Registration macro's w.r.p.t System Verilog version of UVM, & the question If we are not registering the class with a factory using macro then what do we have to do in that case?    • Concept of Factory and Factory Overriding ...   https://edaplayground.com/x/VSt4 #faq #uvm #interviewquestion #semiconductor #verification #factory #factorymacro's #digitalverification #uvmfactory