Objection mechanism w.r.p.t System Verilog version of UVM

This video is all about the concept of the Objection mechanism w.r.p.t System Verilog version of UVM.    • UVM Phases(Build_phase to Final_phase).   One of the FAQs is, Explain raise_objection and drop_objection. EDA PlaygroundFAQs link:- https://edaplayground.com/x/K2ih #vlsi #uvm #faq #interviewquestion #semiconductor #verification #electronicengineerin #systemveriloguvm #objectionmechanism #raiseobjectionanddropobjection