DDR5 Full flow from AXIVIP to DDRIP to DRAMVIP Simulation waveform explanation.

DDR5 6400MT/s, 64 byte Write and read transaction. Step1: AXI vip sending write transaction How exactly those write transaction will travel from AXI to DDRIP and DDRIP to DRAM VIP. Step2: AXI VIP sending read request. How exactly read transaction will travel from DRAM to AXI Also need to compare write data and read data in AXI Interface.