64K RAM & ROM Module for the Breadboard TTL CPU - Part 1

I am upgrading my breadboard 8-bit TTL CPU from Ben Eater's original SAP-1 design to something more. This video is part one of a two part series documenting my work on expanding the memory space for the CPU from the 16 bytes found in the original SAP-1 to 65,536 (64K) bytes evenly split between RAM and ROM. This video focuses on the memory module's design and implementation. In order to expand the memory to the Ben Eater SAP-1 as described in this video, you need to have increased the number of control lines the SAP-1 breadboard computer has, as described in my prior video:    • Adding More Control Lines to the Ben Eater...   Detailed schematics and design information for this project can be found at my GitHub repository: https://github.com/michaelkamprath/ea... My 8-bit TTL CPU is based on the excellent TTL CPU project by Ben Eater. More information about his project can be found here: https://eater.net/8bit If you end up building this design into our breadboard computer, I would love to hear about it!