Review of Server PCB Layout & Schematic - Part 4: PCI Express (PCIE)
This video is about: Zig-Zag routing, Stitching VIAs, Stub in PINs, Holes in GND under PADS and around VIAs, Port 80 & POST Codes Project Olympus: https://www.opencompute.org/wiki/Serv... Files - Olympus Intel: http://files.opencompute.org/oc/publi... Cadence document: https://www.cadence.com/content/dam/c... 100Gbps design guidlines document: https://www.intel.com/content/dam/alt... Would you like to support me in what I do? It's simple: you will help me a LOT, when you sign up for one of our Schematic and PCB Design online courses at https://www.fedevel.com/academy/ The other ways to support me in what I do are: support me through Patreon page / robertferanec sign up for my Udemy course, Learn to Design Your Own Boards https://www.udemy.com/learn-to-design... send me an email and/or leave a positive comment watch and like the videos :) read my Welldone Blog at https://www.fedevel.com/welldoneblog/ spread a word about FEDEVEL Academy It is much appreciated. Thank you, Robert
Review of Server PCB Layout & Schematic - Part 5: SFP 10Gb/s Interface
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