구글 TPU에 삼성 2nm? 삼성 파운드리 본격 부활의 핵심은 칩렛, 메모리 인터페이스 | AI 칩이 쪼개지는 이유

We examined reports regarding Samsung and Google’s TPUs not merely as a battle for foundry orders, but from the perspective of changes in AI chip architecture. In these reports, Samsung was mentioned as a candidate for the memory interface component, rather than the entire TPU. However, in AI accelerators, the memory interface is not merely a peripheral component; it is a critical area that determines the bottleneck between the compute die and HBM. Through discussions on the massive die size and reticle limits of the NVIDIA V100, we also explored why it is becoming increasingly difficult for AI chips to grow larger using only a single die. As chips grow larger, yield, process optimization, memory bottlenecks, and supply chain issues all increase simultaneously. Therefore, AI semiconductors are increasingly shifting toward a chiplet structure that separates the compute die, memory interface, I/O, HBM, and packaging. By also looking at examples of Intel's tile structure and advanced packaging, we explained that this shift has already begun across the industry. The key opportunity for Samsung is not to directly snatch away TSMC's main die, but to enter the bottleneck between memory and logic. We also covered why Samsung’s position, possessing HBM, DRAM, NAND, SSD controllers, CXL, and packaging all in one, could become important again. The key point of this news is not that “Samsung has acquired Google’s TPU,” but rather that it signals a new gateway for Samsung in the chiplet era. Written by Patch Edited by Lee Jae-hyun [email protected]