RISC-V IOMMU Architecture Overview - Perrine Peresse

RISC-V IOMMU Architecture Overview - Perrine Peresse The Input-Output Memory Management Unit (IOMMU) is an essential component in between an IO device and a memory controller that translates device virtual addresses into physical addresses. This talk will introduce the IOMMU Task Group’s charter. It will then describe the IOMMU usage models in a SoC and provide an overview of the initial version of the IOMMU architecture. The presentation will end with the task group status and future challenges.