Basic Static Timing Analysis: Timing Concepts - Net Delay

​The interconnect provides the timing arc from pin to pin and has an inherent delay. This delay is because of the resistance and capacitance of the interconnect. In this content, you Identify wire-load models to calculate net delays Identify the file formats used in backannotation To read more about the course, please go to: https://www.cadence.com/content/caden... For more information about our courses, visit: http://www.cadence.com/training For general Product Support, visit http://www.support.cadence.com Find more great content from Cadence: Subscribe to our YouTube channel:    / @cadencedesignsystems   Connect with Cadence: Website: http://www.cadence.com Facebook:   / cadencedesign   LinkedIn:   / cadence-design-systems   Twitter:   / cadence   About Cadence Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s Intelligent System Design strategy helps customers develop differentiated products—from chips to boards to intelligent systems—in mobile, consumer, cloud data center, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at www.cadence.com.