How to Program an Altera CPLD Logic Chip From 1998 that's in JTAG LOCKOUT ? [#61]
In this video I go over the process of building a simple Digital-electronics circuit to Drive a 7-Segent Display that counts up from 0 to 9 and then halts the counting sequence. We use both 7400 series chips (Integrated Circuits) as well as an Altera CPLD. We use an old Altera CPLD model EPM7064SLC44 programmable logic chip from 1998 that serves as one of the logic devices in the circuit design. We go over the process of programming the Altera MAX 7000 "S" series Complex Programmable Logic Device that is in a state known as "JTAG LOCKOUT". This particular MAX7000 device has an onboard programming interface called JTAG. You use a USB programming pod called the Altera USB-Blaster to program the device over this interface. Now, "JTAG LOCKOUT" is a condition when the device has been previously programmed and the JTAG interface pins on the chip itself; have been reproposed to serve as additional I/O pins as part of a design. This is an available secondary feature for these pins. It provides design Engineers with 4 extra I/O pins to use in there designs. A great feature to have. The unfortunate reality when the JTAG pins are re-assigned in this manner...is that as soon as you program the device, the JTAG programming functionality is then disabled. The chip can no longer be re-programmed by a JTAG programmer. So you are essentially burning the bridge behind you.... so to speak. The only way to re-enable the JTAG programming functionality on the device (ISP) is to ERASE it using a NON-JTAG programming system. These systems are known as Universal Programmers. Most commonly used to program and erase EPROM/EEPROM and Flash memory devices. Altera also had their own proprietary programming system known as the Altera MASTER PROGRAMMING UNIT or "MPU" for short. Model Number PL-ASAP2 was their most popular system that used an ISA Logic Programming Card and was released in the early 90's. There was also a USB version called the Altera PL-APU which was released in the early 2000's. Now after that history lesson lol .... ^_^ During the Filming of this video I accidentally short circuited the Altera CPLD. I therefore decided to use a larger 84 pin Altera CPLD to complete the circuit. I used the Altera MAX7000S device model number EPM7128SLC84. This was another JTAG compliant device. In the last part of the video, I domo the functioning digital circuit, that used both 7400 series integrated circuits as well as the Altera MAX CPLD. Tinkering with Digital-Electronics is Loads of Fun! :)D Cheers! Want to help support my work? Become one of my dedicated Supporters: https://www.behindthecode.ca/become-a-supp... Follow me here: https://linktr.ee/BehindTheCode_wGerry ****************************************************************************** Thanks for visiting Behind The Code with Gerry! ****************************************************************************** #electronics #engineering #Altera #CPLD #FPGA #90s #retrogaming #gamedev #flashcart #nintendo #gamedevelopment #videogames
![Logic Analyzer Capture of an Altera MAX EPM7128SLC84 CPLD Erase Sequence [#65]](https://i.ytimg.com/vi/-Q-mtVItndY/hqdefault.jpg?sqp=-oaymwEjCNACELwBSFryq4qpAxUIARUAAAAAGAElAADIQj0AgKJDeAE=&rs=AOn4CLBqRYfqV9-jCxNW6z4jGGMPPKOWFw)
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Gerry Builds a Custom Adapter to Help Decipher a 90's Era Altera MAX CPLD Erase Sequence [#64]

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