Why is pMOS is good to pass logic 1 and nMOS is good to pass logic 0? | VLSI by Engineering Funda

Why is pMOS is good to pass logic 1 and nMOS is good to pass logic 0? is explained with the following timecodes: 0:00 - VLSI Lecture Series. 0:25 - Basics of Logic in digital circuit 1:05 - nMOS working (nMOS is good to pass logic 0) 6:05 - pMOS working (pMOS is good to pass logic 1) 10:22 - CMOS Circuit by nMOS and pMOS Following points are covered in this video: 0. Complimentary Metal Oxide Semiconductor, CMOS 1. pMOS and nMOS 2. Why is pMOS is good to pass logic 1 and nMOS is good to pass logic 0? Chapter-wise detailed Syllabus of the VLSI Course is as follows: Chapter-1 Introduction to VLSI Design:    • Introduction to VLSI Design   Evolution of Logic complexity, VLSI Design methodologies, Full Custom design and Semi Custom design, VLSI terminologies, Package Technology of IC, VLSI Design flow, Importance of CAD tools in VLSI, Comparison of FPGA, CPLD, PLC, DSP, Microcontroller and Microprocessor. Chapter-2 CMOS Fabrication:    • CMOS Fabrication   CMOS Fabrication process, Twin Tube CMOS Fabrication Process, Photolithography, Ion Implantation. Chapter-3 MOS and MOSFET:    • MOS and MOSFET   Two Terminal MOS structure, Flat band voltage, MOS under external bias, MOSFET, Threshold voltage of MOSFET, Gradual Channel Approximation of MOSFET, Channel Length Modulation of MOSFET, Substrate Bias Effect in MOSFET, MOSFET Capacitances, nMOS and pMOS, Examples on MOS, MOSFET, nMOS and pMOS. Chapter-4 MOS Inverter:    • MOS Inverter   nMOS Inverter, Noise Margin and Transfer characteristics of nMOS Inverter, Resistive Load Inverter, Depletion Load nMOS Inverter, CMOS Inverter, Voltage Transfer characteristics of CMOS Inverter, Parameters of CMOS Inverter, Examples on CMOS Inverter, Propagation delay of CMOS Inverter. Chapter-5 CMOS circuits:    • CMOS circuits   CMOS Circuits rules, CMOS NAND gate, CMOS NOR gate, Boolean function using CMOS, CMOS Multiplexer, CMOS SR Latch using NOR gates, CMOS SR Latch using NAND gates, CMOS D Latch, CMOS SR Flip Flop using NOR gates, CMOS JK Flip Flop using NOR gates, Stick Diagram, CMOS Transmission Gate, Multiplexer using Transmission gates, D Latch using Transmission gates, Boolean function implementation using transmission gates. Chapter-6 Advanced CMOS:    • Advanced CMOS   Dynamic CMOS, Cascading issues of dynamic CMOS, Comparison of static CMOS and Dynamic CMOS, Domino Logic CMOS, Charge sharing in Dynamic CMOS, Boolean function implementation using dynamic CMOS, NORA CMOS logic, Boolean function implementation using NORA CMOS, Voltage Bootstrapping, Latch Up in CMOS and Latch up prevention steps, FinFET Technology. Chapter-7 Clock, Fault and Testing of VLSI:    • Clock, Fault and Testing of VLSI   On Chip Clock Generation, Ring Oscillator, Clock Distribution, Faults in Integrated circuits, BIST - Bult In Self Test in Integrated circuit, Stuck at Fault. Chapter-8 Verilog VHDL Programming:    • Verilog VHDL Programming   Engineering Funda channel is all about Engineering and Technology. Here this video is a part of VLSI. #VLSI #VlsiDesign #EngineeringFunda @EngineeringFunda