Time Appliances Project Call #161 (June 17, 2026)

Abstract: As precision‑timing requirements expand beyond traditional telecom infrastructure into hyperscale datacenters, edge sites, and other critical environments, distributing both frequency and absolute phase with deterministic behavior is increasingly constrained by pin count, cabling complexity, and calibration overhead. Conventional approaches that route separate 10 MHz and 1PPS signals amplify skew sensitivity across connectors, cables, and dense platform topologies, creating operational risk and limiting scalability. This talk presents Embedded Pulse‑Per‑Second (EPPS), a physical‑layer technique that embeds a precise one‑second phase marker directly into a 10 MHz reference using controlled duty‑cycle modulation while remaining compliant with established electrical interfaces. Frequency and phase are intrinsically aligned at the source, and receivers recover continuous frequency and discrete time through straightforward detection and DPLL processing—eliminating ambiguity introduced by separate signal paths. I will describe the EPPS waveform characteristics, detection and recovery considerations, and architectural implications for resilient deployment inside racks and servers. The discussion emphasizes how a single deterministic interface can reduce wiring complexity, minimize skew accumulation, and simplify system bring‑up in dense environments. Where possible, I include representative bench results illustrating marker detectability and recovered timing behavior over short‑reach copper interconnects typical of real deployments. By treating phase distribution as a physical‑layer problem rather than a protocol extension, EPPS provides a scalable and standards‑aligned approach to resilient synchronization across modern infrastructure domains. Speaker: Greg Armstrong has dedicated 30 years to the Telecommunications industry, excelling as a System Architect, Application Engineer, and Embedded Software Engineer. As a Principal System Architect within the Timing Division at Renesas Electronics—following its acquisition of Integrated Device Technology (IDT) in 2019—Greg leads the technical definition of innovative timing products and develops product roadmaps for both silicon and software solutions. He also represents Renesas in the IEEE P1588, IEEE P3335, and ITU-T SG15/Q13 working groups. With over 19 years of experience in synchronization technologies, Greg’s expertise includes frequency, phase, and time synchronization over packet networks, such as SyncE, IEEE 1588, NTP, ToP, RTP, and CESoPSN. He also has a strong background in Ethernet/IP switching and 10G SDH/SONET/ETH Framers/Mappers. Greg has shared his knowledge with System Architects and Design Engineers at leading companies, presented at major industry conferences, and holds patents in clocking technologies. Beyond his technical achievements, Greg is a member of the Workshop on Synchronization and Timing Systems (WSTS) Steering Committee and serves on the International Timing and Sync Forum (ITSF) Advisory Board. Since 2016, he has delivered tutorials on Phase-Locked Loops (PLLs) and O-RAN Synchronization Fundamentals at both ITSF and WSTS conferences. Greg earned a degree in Electronic Systems Engineering from the University of Regina, Canada, in 1995, launching his career at Bell Northern Research (Nortel Networks) in Ottawa, Canada.