A Silicon-Proven Unified Low-Latency CXL Controller and Port-Based Routing Switch (ISCA 2026)

Check Out This Presentation Video Introducing Our Silicon-Proven, Next-Stage CXL Solution! At ISCA 2026 (International Symposium on Computer Architecture), two demonstrations of CXL’s practicality were presented—one by #Meta and one by #Panmnesia. Panmnesia, a fabless startup, validated the performance of its own silicon-based CXL controller and switch. Separately, Meta, a global hyperscaler, unveiled the results of a real-world deployment of CXL silicon chips in its own data centers. Bringing the two demonstrations presented at this year's ISCA together, we can conclude that—across the entire path, from controller and IP (intellectual property) design to silicon implementation, routing, operating-system support, and large-scale deployment—CXL is ready for practical use in the data center. This video covers parts of Panmnesia's demonstration. In short, Panmnesia showed that its next-stage CXL controller and PBR (Port-Based Routing) switch—both design-optimized and built in real silicon—keep memory-access latency low while significantly extending memory expansion to span dozens of servers or more. Note that the next-stage CXL controller and PBR switch introduced in this presentation have since been further advanced and are now available. For inquiries: https://panmnesia.com/contact/ Talk Title: "A Silicon-Proven Unified Low-Latency CXL Controller and Port-Based Routing Switch for Memory-Centric Fabrics" Presenter: Yongjin Cho, CPO of Panmnesia Presented at: Industry Session / ISCA 2026 / Raleigh, USA