Experiment 6: JK Flip flop using Static cmos gates Cadence virtuoso

Specifications: Vpulse(J): V1 = 1.2 V Period = 20n s Pulse width = 10n s Vpulse(k): V1 = 1.2 V Period = 30n s Pulse width = 15n s Vpulse(CLK): V1 = 1.2 V Period = 40n s Pulse width = 20n s Vdc = 1.2 V(DC) trans: 100n Note: the noise you will see in Q and Qb are the toggles created when J,K,CLK=1 to clear the toggle you can add delay in K by 10n s and take period as 20n s with pulse width = 10n s