SystemVerilog Assertions CLOCK DELAY OPERATOR with and without range

This is part of a series of lectures on SystemVerilog Assertions by Ashok B. Mehta. The entire class is available on Udemy. 50 Lectures; 12 hours; Lifetime access (once you purchase, you can view it whenever for eternity!). https://www.udemy.com/course/systemve... This lecture explains the clock delay operator, both without and with range. More importantly, how can you end up getting a False Positive with the clock delay range operator?