RISC-V Assembly Code #5: RV32 v RV64
A multipart series describing the RISC-V core (RV32, RV64) and its assembly language. We describe the ISA, registers, and instructions and cover some optional extensions. This episode describes the differences between 32 and 64 bit cores, i.e., the differences between RV32I and RV64I.
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RISC-V Assembly Code #6: Multiply, Divide Instructions
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Making Smallest Possible Linux Distro (x64)
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RISC-V Assembly Code #1: Course Intro, Registers
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RISC-V 2026 Update
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Rust and Memory
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How Huawei Just Built an Impossible Chip
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RISC-V: Verilog Implementation (FemtoRV)
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The Design of C++ , lecture by Bjarne Stroustrup
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Co-Creator of Haskell: Why Learn Functional Programming, Useless vs Useful Languages | Simon Jones
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The "Trick" that Compilers Use for Long Division - Computerphile
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Something is jamming GPS over Europe. Here's what we found
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Why Some Low-Level Projects Are Full of Weird Code Like This
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How Much Memory for 1,000,000 Threads in 7 Languages | Go, Rust, C#, Elixir, Java, Node, Python
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How to Actually Learn C (2027 Edition)
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How CPUs Interact with So Many Different Devices
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How Nuclear Power Works
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you can learn assembly in 10 minutes (try it RIGHT NOW)
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The AI Take Over Has Completely Backfired and I Can't Be Happier
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