BECL606 ECE Lab | Four-Bit Synchronous MOD-N Counter with Reset

Welcome to the *VLSI Design and Testing Laboratory (BECL606)* experiment series conducted by the **Department of Electronics and Communication Engineering, ATME College of Engineering, Mysuru**. In this video, we demonstrate the **Design and Verification of a Four-Bit Synchronous MOD-N Counter using Verilog HDL**. The objective of this experiment is to design a four-bit synchronous MOD-N counter with reset functionality, verify its operation using a dedicated testbench, synthesize the design to generate the gate-level netlist, and analyze synthesis reports to determine important performance parameters such as **critical path, timing delay, power consumption, and area utilization**. 🔍 Topics Covered: ✅ Introduction to Counters and MOD-N Counters ✅ Verilog HDL Implementation of a Four-Bit Synchronous MOD-N Counter ✅ Understanding Reset Functionality ✅ Testbench Development and Functional Verification ✅ RTL Simulation and Waveform Analysis ✅ Synthesis and Gate-Level Netlist Generation ✅ Timing Report Analysis ✅ Area Utilization Evaluation ✅ Power Consumption Estimation ✅ Critical Path Identification 🎯 Learning Outcomes: • Understand the working principle of synchronous counters. • Design and implement a four-bit MOD-N counter using Verilog HDL. • Verify counter functionality using simulation waveforms. • Develop testbenches for functional verification. • Analyze synthesis reports related to timing, area, and power. • Gain practical exposure to the digital ASIC design flow. • Understand the importance of reset mechanisms in sequential circuits. --- 🏫 *ATME College of Engineering, Mysuru* 📚 *Department of Electronics and Communication Engineering* 🎓 *Course:* VLSI Design and Testing Laboratory 📖 *Course Code:* BECL606 🗓️ *Semester:* VI Semester 👨‍🏫 *Guided by:* *Chandra Shekar P* Assistant Professor Department of Electronics and Communication Engineering ATME College of Engineering, Mysuru --- 🔔 If you found this video useful, please *Like, Share, and Subscribe* for more laboratory demonstrations, Verilog HDL tutorials, and VLSI design concepts. 📚 BECL606 Experiment Series: ▶️ Experiment 1 – Design and Verification of a 4-Bit Adder ▶️ Experiment 2 – Design and Verification of a 4-Bit Shift-and-Add Multiplier ▶️ Experiment 3 – Design and Verification of a 32-Bit Arithmetic Logic Unit (ALU) ▶️ Experiment 4 – Design and Verification of D, SR, and JK Flip-Flops ▶️ Experiment 5 – Design and Verification of a Four-Bit Synchronous MOD-N Counter #BECL606 #VLSI #VerilogHDL #MODNCounter #SynchronousCounter #DigitalDesign #ASICDesign #RTLDesign #SequentialCircuits #ECELab #ATMECollege #ECE #VLSILaboratory #EngineeringEducation #Mysuru #VLSILabExperiment5