ASIC | Digital Interview Questions | ASIC design | RTL to GDSII | Difference in ASIC and FPGA flow

In this video, I discuss the ASIC design flow, from defining specifications to generating the GDSII file for fabrication. I cover key stages such as RTL design, logic synthesis, verification, placement, routing, and post-layout verification to optimize performance and efficiency. Finally, I explain the sign-off checks that ensure the design is ready for manufacturing. This video also explains difference in ASIC and FPGA flows. Synthesis Static Timing Analysis FPGA (Field Programmable Gate Array)