Every Chinese Memory Chip Is Designed on American Software. Beijing Just Found the Door

Before a single gas flows into a chamber, a DRAM chip exists only as a file — and that file speaks a language two American companies wrote. Every Chinese memory chip that shipped last year passed through it. Every one. I traced one DRAM cell's design file across the invisible network beneath the silicon — schematic entry to a Chinese fab's mask set — and read the dependency map node by node. Not the machines you can photograph, but the chokepoints you can't: the file formats, the process design kits every fab writes against, and the verification sign-off that turns a layout into a legal mask. Here's what each node actually shows. Design entry & the process design kit — Sealed. Every CXMT layout is drawn to Cadence and Synopsys interchange formats. A Chinese-native schema would need every IP vendor, library, and verification tool to switch at once — and that coordinated switch hasn't happened. Place-and-route — Bypass under construction. Advanced physical design still runs on Synopsys IC Compiler and Cadence Innovus. Empyrean has disclosed physical-design wins, but only at mature nodes so far. Physical verification & foundry sign-off — The sharpest lock on the board. Design-rule check, layout-versus-schematic, and parasitic extraction are certified against Synopsys Calibre and Cadence's suite; domestic tools like Primarius are in qualification, not production sign-off — and that gap is measured in tape-out cycles, not press releases. The domestic challengers — Real, but bounded. Empyrean and Primarius are proven at DDR4-generation geometries, analog and mixed-signal, and library work. No independent source has confirmed a full-flow advanced tapeout with zero Cadence or Synopsys in the certified path. The node the file can't pass — The full-flow advanced sign-off. It's a funnel, not a wall: closing, but not closed. The finding: China has rerouted the mature segments of the electronic design automation (EDA) map faster than most Western coverage admitted — the mature-node bypass is real. But the leading-edge verification sign-off, the step that converts a layout into a legal mask, remains the most durable chokepoint, because it's a trust-and-time barrier that compounds with every process generation. Two different maps: meaningfully self-contained at the mature edge, nowhere near it at the leading edge — and conflating them is the most common error in this story. Players under it all: Cadence, Synopsys, Empyrean, Primarius, CXMT, YMTC, SMIC, and U.S. Commerce Department export controls on EDA software. What I'm watching next: whether any Chinese foundry publicly certifies a domestic design-rule-check tool for a sub-20nm DRAM node in the next 18 months. If it does, the map changes. Which node do you think falls first — and what would it take? Comments below. Subscribe and turn on notifications for the next node.