Why are RISC-V Immediates so weird?
RISC-V Imediates feature this weird bit of Swivling in the way that immediate are encoded. In this video, I discuss some aspects of CPU design to understand why they are encoded this way. 0:00 Problem Statement 1:52 RISC vs. CISC & Instruction Decode 5:07 Reason #1: Minimizing the number of Multiplexers 8:12 RISC-V solution seems to be slightly sub-optimal 10:25 Fanout 15:25 Reason #2: Making Sing Extending easier 19:10 Conclusion
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