The S-R Latch and S'-R' Latch: Cross-Coupled Feedback That Remembers

The first real memory element in digital logic: a latch built from cross-coupled gates. This video walks through the S-R latch (cross-coupled NOR) with a live interactive, then the S'-R' latch (cross-coupled NAND) — and in both cases shows that the feedback path is what makes the stored bit persist. For the S-R latch, remember the wiring as "Q pairs with R, and S pairs with Q-bar." Setting S=1 drives Q-bar to 0 and forces Q=1; then when you remove the set signal, the fed-back 1 holds Q=1 all by itself — that feedback is the memory. Reset (R=1) is the mirror image. Asserting both S and R at once is the forbidden state: nothing breaks, but releasing them together races to an unpredictable result, so we don't do it. The S'-R' latch works on the same principle with cross-coupled NAND gates and active-low ("low true") inputs: you set by driving S' to 0, reset by driving R' to 0, and the resting/hold state is S'=R'=1. NAND is the traditional way to build a latch, and — more importantly — the S'-R' latch is the stepping stone to the D (data) latch, where set/reset give way to "store this data when enabled." Chapters: 0:00 Cross-coupled NOR gates as a memory element 0:18 The wiring mnemonic: Q pairs with R, S pairs with Q-bar 0:51 Q-bar vs QN: a technicality 1:20 Set — S=1 stores a 1 2:05 Memory — remove the signal and the feedback holds it 3:07 Reset — R=1 clears it 4:39 The forbidden state (S=R=1) and the race condition 5:24 The S'-R' latch: cross-coupled NAND, active-low 5:40 Set = drive S' low; resting state S'=R'=1 6:27 Reset = drive R' low 6:56 Why S'-R'? NAND tradition, and the road to the D latch Part of the Digital Logic Infobook: https://bigmikeprojects.github.io/digital-...