ASIC DESIGN- LOGIC SYNTHESIS & PHYSICAL DESIGN USING SYNOPSYS DC AND ICC

This video presents the final group project of our ECE 581 ASIC Modelling and Synthesis course, done by myself (Melvin Sen Thomas), Nancy Rachel Mathen and Saurabh Rabade, all students of Portland State University ECE Department. This video walks through the steps from RTL Design to Logic synthesis and physical design using Synopsys Tools including the various steps involved in PD like floorplanning, P and R, CTS etc using Synopsys Design Compiler and Synopsys IC Compiler. Formal Equivalence verification is done using Cadence Conformal Tool. Do leave you comments below and if you like the video don't forget to give a thumbs up if it helped you in your course!