Compile and Run Simulation in Quartus Prime for Verilog and VHDL RTL Codes with Testbench and Questa
#Compile and #Run #Simulation in #Quartus Prime for #Verilog and #VHDL #RTL #Codes with #Testbench and #questa SV RTL code: module and_gate (a,b,c); input a,b; output c; and (c,a,b); endmodule SV RTL testbench: module test; reg a,b; wire c; and_gate dut(a,b,c); initial begin #0 a=0;b=0; #10 a=0;b=1; #10 a=1;b=0; #10 a=1;b=1; #10; end endmodule VHDL RTL code: library IEEE; use IEEE.std_logic_1164.all; entity and_gate is port(a : in std_logic; b : in std_logic; c : out std_logic); end and_gate; architecture behav of and_gate is begin c ＜= a AND b; end behav; VHDL RTL testbench: library IEEE; use IEEE.std_logic_1164.all; entity test is end test; architecture behav of test is component and_gate is port(a : in std_logic; b : in std_logic; c : out std_logic); end component; signal a,b,c :std_logic; begin dut: and_gate port map(a,b,c); process begin a＜='0'; b＜='0'; wait for 10 ns; a＜='0'; b＜='1'; wait for 10 ns; a＜='1'; b＜='0'; wait for 10 ns; a＜='1'; b＜='1'; wait for 10 ns; wait; end process; end behav;
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