Latch-up in CMOS Technology | Latch-up Formation & Triggering | Issues in Physical Design
Latch up issue in CMOS technology has been explained in this video. Formation of parasitic BJT in CMOS process has been explained first then latch-up triggering mechanism has been explained with the help of cross-section schematic and layout of CMOS. Latchup prevention will be explained in next session. If you feel this video is relevant to your domain and useful, please like the video and subscribe to this channel. Your queries/suggestions are most welcome in the comment section. ---------------------------------------------- VIDEOS IN THIS SERIES 1. Latchup issue: • Latch-up in CMOS Technology | Latch-up Fo... 2. Latchup prevention techniques • Latch-up prevention in CMOS | Various tech... 3. Antenna effect: • Antenna effect in VLSI Fabrication | Plasm... 4. Antenna prevention techniques • Antenna Effect Prevention Techniques in VL... 5. Electromigration issue in ASIC • Electromigration in VLSI Design | What is ... 6. IR Drop Issue in VLSI • IR Drop issue in VLSI | What is IR drop in... 7. On-Chip variations • On-Chip Variation in VLSI | OCV | Why OCV ... 8. Crosstalk effect in VLSI • Crosstalk issue in VLSI | Signal Integrity... 9. Crosstalk prevention • Crosstalk issue and prevention techniques... ------------------------------------------------------------------------------ Connect with us All on one page: https://www.teamvlsi.com/p/contact_8.... Blog: https://www.teamvlsi.com Facebook Page: / teamvlsi WhatsApp Group: https://chat.whatsapp.com/C6etLHR6oAf... Telegram Group: https://t.me/teamvlsi (Or search team VLSI on telegram) Email: [email protected] #Latchup #LatchupInVLSI #LatchupIssue
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