Overview of Static Timing Analysis in OpenSTA - Akash Levy

Static timing analysis (STA) is critical for ensuring that a chip will behave as expected post-tapeout. In this talk, I will give a brief intro to the basic concepts in STA, and will provide examples in OpenSTA, the leading open-source tool in VLSI timing/power analysis. I will talk about the implementation of Synopsys Design Constraints (SDC) and Liberty Non-Linear Delay Model (NLDM) with examples. I will finally discuss how OpenSTA can be bolted onto other tools as a robust timing engine.