Reset Domain Crossing for Designs With Set-Reset Flops
Presented at DVCon U.S. 2021 There are cases where the Reset Domain definition is not that simple and straight forward. One such case is the handling of “Set-Reset” flops. We face design features where there is more than one asynchronous set/reset controlling a flop. This paper specifically explores the different possible scenarios with such flops and problems introduced by these in the RDC closure. Which potentially can be dangerous and time consuming. By: Abdul Moyeen, Siemens EDA Inayat Ali, NXP Semiconductors https://dvcon.org https://dvcon-proceedings.org
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