ECE 165 - Lecture 7: Layout and Combinational Logic I (2021)
Lecture 7 in UCSD's Digital Integrated Circuit Design class. Here we introduce the basics of doing layout - or physical design - in modern CMOS processes. We use an open-source 45nm PDK in this example. With this understanding of layout, we then introduce techniques to help improve the speed of designs through input ordering, asymmetric gates, skewed gates, and combinational path optimizations. We conclude with a rule-of-thumb for fan-in and fan-out.
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ECE 165 - Lecture 8: Combinational Logic II (2021)
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ECE 165 - Lecture 13: Dynamic Logic (2021)
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Integrated Circuit Layout Design Techniques 1 (English Version): Introduction to Layout Design
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ECE 165 - Lecture 4: MOS Capacitances and Delay (2021)
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ECE 165 - Lecture 6: Logical Effort & Timing Optimization (2021)
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Building logic gates from MOSFET transistors
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4.7 - Logical effort and Parasitic delay
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IC Design I | Finding CMOS Schematic from a simple layout
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