VLSI Physical Design: Clock Tree Synthesis (CTS)
website: https://www.vlsi-backend-adventure.co... clock tree synthesis -Difference between HFNS and CTS -Why buffer/inverters are inserted? -Difference between clock buffer and normal buffer -Inputs of clock tree synthesis (CTS) -Sanity checks before CTS -Goals of CTS -Clock latency -The clock problem -Main concerns for clock design: skew, power, noise, delay -Clock skew: positive skew, negative skew, local skew, global skew, boundary skew, useful skew. -Clock Jitter -CTS pre-requisites -CTS Objects -CTS Flow -Clock tree references: boundary cell insertion, delay insertion -Clock Tree Exceptions: Non stop pins, exclude pins, float pin, stop pin, don't touch sub-tree, don't buffer net, don't size net. -CTS Algorithm -Analyze the clock tree -Post CTS optimization -CTS outputs -
DVD - Lecture 8: Clock Tree Synthesis
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Clock Tree Synthesis (CTS)
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