Use VS Code for RTL Design with Vivado | VHDL + SystemVerilog End-to-End Workflow

In this video, I show a complete FPGA RTL development workflow using VS Code as the editor and Vivado tools for linting, simulation, and project creation. You will learn: How to configure real-time syntax checking in VS Code How to enable Go To Definition (F12) with CTags How to run mixed-language simulation (VHDL + SystemVerilog) using Makefile How to create a Vivado project from a Tcl script and filelists Visual Studio Code extensions used in this project: Verilog-HDL/SystemVerilog/Bluespec SystemVerilog Ctags Companion Project files used in this video: .vscode/settings.json .vscode/tasks.json scripts/Makefile scripts/filelist_sv.f scripts/filelist_vhdl.f scripts/filelist_tb.f scripts/create_project.tcl GitHub repository: https://github.com/aiclab-official/vs... 03:09 Real-Time Syntax Errors in VS Code 04:29 Enable F12 Go To Definition with CTags 06:11 Simulation Flow with Makefile 07:15 Open Waveform 07:31 Create Vivado Project from Tcl