Next big step for Verilator: towards four-state logic and UVM compatibility (Krzysztof Bieganski)

Building on our ORConf 2025 verification in Verilator (https://fossi-foundation.org/orconf/2...) presentation, in this talk we'll dive into further progress Antmicro and others have made with regard to Verilator's verification capabilities. We will cover topics like improvements to UVM compatibility, developments in assertion support, an overhaul of force/release statements, and the next big step for Verilator: four-state logic. We will also touch on tools that helped us get here, such as sv-bugpoint or CHIPS Alliance's sv-tests.