First Steps with UVM Part 2
Doulos co-founder and technical fellow John Aynsley presents a simple, complete SystemVerilog UVM source code example (which you can run on http://www.edaplayground.com/x/UDv), explaining what is happening and highlighting best practice. You are shown how to drive pins on the design-under-test interface from the UVM verification environment, and how to pass a virtual interface using the configuration database. Some further examples: http://www.edaplayground.com/x/WPG http://www.edaplayground.com/x/UXT http://www.edaplayground.com/x/Nht This is just one of a series of UVM tutorials, watch the rest of the playlist here: • Easier UVM Video Tutorial Doulos provides scheduled classes online and in-person & delivers on-site team-based training & interactive online learning events worldwide – you can find out the very latest on our website: https://www.doulos.com POPULAR UVM TRAINING UVM Adopter Class: https://bit.ly/45XXQax Comprehensive SystemVerilog : https://bit.ly/3PaOVfK To enquire about training for you, or for your team : https://bit.ly/3WZ9a1W Subscribe to our channel, @DoulosTraining, for more: Introductory videos to range of our most popular training topics – System Verilog, UVM, SystemC & TLM-2.0, VHDL, Python & Deep Learning, & Arm. Answers to common questions & “how to’s ”. Our latest live & on-demand webinars (& joining links). Subscribe (and set your notifications): https://bit.ly/3MYWzsk Follow us on Twitter: @DoulosTraining Find us on LinkedIn: / doulos-ltd
First Steps with UVM Part 3
First Steps with UVM Part 1
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