sv part1

SystemVerilog data types are divided into 2-state and 4-state categories. A 2-state type stores only 0 and 1 and is mainly used in verification components such as classes, scoreboards, and transaction objects because it provides faster simulation and lower memory usage. A 4-state type stores 0, 1, X (unknown), and Z (high impedance), making it suitable for RTL design, buses, interfaces, and hardware modeling where unknown and tri-state conditions must be represented accurately. Verilog is primarily a hardware description language with basic constructs such as reg and wire, whereas SystemVerilog extends Verilog by adding modern features like logic, classes, inheritance, randomization, constraints, assertions, interfaces, packages, dynamic arrays, queues, and functional coverage, making it the industry-standard language for both design and verification, including UVM-based environments.