A Multigigabit Link Layer Protocol for Single ps Latency Determinism on AMD FPGA (Pablo Trujillo )

In the design and validation of high-speed electrical systems, such as power converters, the fidelity of the electrical model is strictly limited by the minimum achievable time-step. Conventional FPGA-based simulators often operate in the range of microseconds or, at best, several hundred nanoseconds. This limitation can lead to failures in capturing high-speed transients or introduce numerical instabilities caused by the solver constraints. This presentation explores how combining discretized mathematical models with AMD Versal can be leveraged to push real-time simulations down into the nanosecond range. We will first discuss the creation of high-efficiency RTL models for power converters and their conversion into synthesizable block diagrams. Finally, we will demonstrate how by using the Versal architecture, we can enable the execution of these models at high-speeds, even allowing us to offload part of the instrumentation and measurement logic directly into the FPGA design.