Knowledge Engineering-First Order Logic-Artificial Intelligence-15A05606-Unit-2-Logical Reasoning

Unit – 2 – Logical Reasoning First Order Logic / Predicate Logic – Part-III - Knowledge Engineering Knowledge Engineer is someone who investigates a particular domain, learns what concepts are important in that domain, and creates a formal representation of the objects and relations in the domain. General purpose knowledge base Support queries about full range of human knowledge. In this we can expect any kind of query, which knowledge base will have to infer. Special purpose knowledge base Which has restricted domain (problem specific), here expected queries are known in advance. Steps in Knowledge Engineering Process Identify the task Assemble the relevant knowledge Decide on a vocabulary of predicates, functions, and constants Encode general knowledge about the domain Encode a description of the specific problem instance Pose queries to the inference procedure and get answers Debug the knowledge base 1. Identify the task. Identify the task similar to PEAS design. Knowledge engineer must describe the range of question that the KB will support Find the facts that available for each specific problem instance Does the circuit actually add properly? (circuit verification) 2. Assemble the relevant knowledge Composed of wires and gates; Types of gates (AND, OR, XOR, NOT) Irrelevant: size, shape, color, cost of gates 3. Decide on a Vocabulary Translate the important domain level concepts into logic level names. Once the choice among predicates, functions and constants have been made, the result is vocabulary, which is Ontology of domain. Type(X1) = XOR Type(X1, XOR) XOR(X1) Type(X2) = XOR Type(X2, XOR) XOR(X2) Type(A1) = AND Type(A1, AND) AND(A1) Type(A2) = AND Type(A2, AND) AND(A2) Type(O1) = OR Type(O1, OR) OR(O1) 4. Encode General Knowledge Of The Domain t1,t2 Connected(t1, t2)  Signal(t1) = Signal(t2) (t=terminal, g=gate) t Signal(t) = 1  Signal(t) = 0, 1 ≠ 0 t1,t2 Connected(t1, t2)  Connected(t2, t1) g Type(g) = OR  Signal(Out(1,g)) = 1  n Signal(In(n,g)) = 1 g Type(g) = AND  Signal(Out(1,g)) = 0  n Signal(In(n,g)) = 0 g Type(g) = XOR  Signal(Out(1,g)) = 1  Signal(In(1,g)) ≠ Signal(In(2,g)) g Type(g) = NOT  Signal(Out(1,g)) ≠ Signal(In(1,g)) 5. Encode The Specific Problem Instance Type (X1) = XOR Type(X2) = XOR Type(A1) = AND Type(A2) = AND Type(O1) = OR Type(C1) = Circuit Connected(Out(1,X1),In(1,X2)) Connected(In(1,C1),In(1,X1)) Connected(Out(1,X1),In(2,A2)) Connected(In(1,C1),In(1,A1)) Connected(Out(1,A2),In(1,O1)) Connected(In(2,C1),In(2,X1)) Connected(Out(1,A1),In(2,O1)) Connected(In(2,C1),In(2,A1)) Connected(Out(1,X2),Out(1,C1)) Connected(In(3,C1),In(2,X2)) Connected(Out(1,O1),Out(2,C1)) Connected(In(3,C1),In(1,A2)) 6. Pose Queries To The Inference Procedure What are the possible sets of values of all the terminals for the adder circuit? i1,i2,i3,o1,o2 Signal(In(1,C1)) = i1  Signal(In(2,C1)) = i2  Signal(In(3,C1)) = i3  Signal(Out(1,C1)) = o1  Signal(Out(2,C1)) = o2 There are substitution of variables i1,i2,i3 with values (1/0). The final query will return complete with given Input and Output for the device. It should be used to check that add inputs correctly This is called as circuit verification. 7. Debug the knowledge base We have to see the knowledge base in different ways System unable to give output in no signals If all inputs are 000, then the output also 00, And etc. May have omitted the assertions like 1 ≠ 0 Subscribe this channel, comment and share with your friends. For Syllabus, Text Books, Materials and Previous University Question Papers and important questions Follow me on Blog : https://dsumathi.blogspot.com/ Facebook Page : https://www.facebook.com/profile.php?... Instagram :   / dsumathiphd