⨘ } VLSI } 19 } System Verilog } Assertions } Protocol Verification } LEPROF }

Assertions for asynchronous interfaces, how asynchronous master-slave protocol assertions can be written, debugged and complex protocols can be verified, are discussed. 1. Master asserts request signal to slave indicating communication initiation, and request signal should get asserted only after N number of clock cycles data signal is stable. 2. Slave's grant signal follows the request of master, that is grant should get de-asserted within N number of clock cycles of de-assertion of request signal from Master. 3. Assertion module. 4. Binding of assertion module to module instances. 5. Assertion controls - helpful for debugging. ERRATA: 1. At time 5:20 I misstated, I was supposed to say grant must have to be de-asserted within 2 clocks of req get de-asserted. 2. There is a mistake in module my_assertion code, it needs to have following. input clk, rst, sel, req, grant, data; please ►Subscribe, thumbs up 👍 and press bell 🔔 appreciate your feedback and support. LEPROF/1LEPROF/LEPROFESSEUR