DVD - Lecture 3e: Liberty (.lib)

Bar-Ilan University 83-612: Digital VLSI Design This is Lecture 3 of the Digital VLSI Design course at Bar-Ilan University. In this course, I cover the basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS). Lecture 3 is the first of two part overview of logic synthesis. The first lecture focuses on Standard Cell Libraries, which are an integral part of the synthesis process. Lecture 3e dives into the nonlinear delay models used for static timing analysis and the Libery (.lib) format, which is the common format to provide timing models. Lecture slides can be found on the EnICS Labs web site at: https://enicslabs.com/academic-course... All rights reserved: Dr. Adam Teman Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs Faculty of Engineering, Bar-Ilan University